Semiconductor integrated circuit devices may be designed to allow simplified failure diagnostic testing. One design technique which allows such testing is referred to as scan path design. In scan path design, circuit elements are arranged to form a series of linked shift registers for diagnostic testing purposes. The bit shift route through these linked shift registers is referred to as a scan path. A bit shift operation is used to serially supply diagnostic test data to each of the linked circuit elements.
Each circuit element in the scan path includes a scan input, in addition to the regular data input and data output for the circuit element. During a scan test operation for a circuit element, the normal operation of the circuit element is inhibited. With scan testing enabled, a signal applied to the scan input of a typical scanable circuit element produces a corresponding scan out signal at the circuit element's data output. A scan out signal may also be provided at a separate scan output. The scan out signal produced by the circuit element in response to the scan in signal should coincide with the signal which would have resulted in the normal operation of the circuit. Failure of the circuit element to produce the predicted scan out signal indicates a failure of the circuit element.
Although the ability to scan test circuit elements in an integrated circuit simplifies diagnostic testing, there have been drawbacks to scan path design. One such drawback is the effect of the additional scan test circuitry on the performance of a circuit element in normal operation. Scan test circuitry associated with a particular circuit element may add substantial capacitance to the circuit element critical path. This added capacitance results in a substantial reduction in the performance of the circuit element in normal operation.